1. Field of the Invention
The present invention relates to a three-dimensional memory module and a semiconductor device which uses the same, and more particularly to a three-dimensional memory module which contains semiconductor memory chips and at least one chip selector chip and a semiconductor device which uses the same.
2. Description of the Related Art
A conventional three-dimensional integrated circuit device which contains a chip selector chip is described in Japanese Laid Open Patent Disclosure (JP-A-Heisei 5-121713). FIG. 1 shows the outline structure of the conventional three-dimensional integrated circuit device.
Referring to FIG. 1, the three-dimensional integrated circuit device has a lamination structure composed of a light sensor layer 41 as a first layer in which a plurality of amplification-type light elements are arranged in a matrix manner, an A/D converter layer as the second layer, and an arithmetic logic processing layer 43 as the third layer. The gate potential of each of the light elements in the light sensor layer 41 is kept at the hole accumulation potential which is accumulation potential due to holes accumulated as the result of the incidence of the light. Therefore, it is possible to read a signal without destroying a hole accumulation quantity, i.e., a data. By the addition of a selection circuit, the three-dimensional integrated circuit device of a full monolithic IC structure is accomplished. In the three-dimensional integrated circuit device, the amplification-type light elements are used to make random access possible such that a signal can be read from an arbitrarily designated one of the light elements arranged in the matrix array.
FIG. 2 shows a block diagram illustrating an example of the structure of the three-dimensional integrated circuit device shown in FIG. 1. Referring to FIG. 2, the three-dimensional integrated circuit device is composed of a light receiving section 20, a horizontal and vertical scanning circuits 21 and 22, a voltage generating circuit 23, a buffer circuit 32, an analog digital converter (ADC) 33, a buffer register 34, a CPU 35, a memory 36, an I/O buffer 37, a timing controller 38, an address decoder 39 and a shutter controller 40.
Because the operation of the circuit device shown in FIG. 2 is not related to the present invention, the detailed operation is omitted.
As described above, the conventional three-dimensional integrated circuit device with a chip selector chip incorporated employs a full monolithic IC structure. Therefore, in order to fabricate the three-dimensional integrated circuit device which has a desired memory capacity, it is necessary to start from the design of the monolithic IC.
Also, when the memory needs to have a capacity more than a memory which is commercially available at the present time, it is necessary to develop a new process for the monolithic IC.
However, the advanced technique, the long development period and the huge resource are needed for the development of a monolithic IC and the development of a new process technique for the monolithic IC.